View LT1792_183724.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT1792 Low Noise, Precision, JFET Input Op Amp
FEATURES
s s s s s s
DESCRIPTIO
100% Tested Low Voltage Noise: 6nV/Hz Max A Grade 100% Temperature Tested Voltage Gain: 1.2 Million Min Offset Voltage Over Temp: 800V Max Gain-Bandwidth Product: 5.6MHz Typ Guaranteed Specifications with 5V Supplies
The LT(R)1792 achieves a new standard of excellence in noise performance for a JFET op amp. The 4.2nV/Hz voltage noise combined with low current noise and picoampere bias currents make the LT1792 an ideal choice for amplifying low level signals from high impedance capacitive transducers. The LT1792 is unconditionally stable for gains of 1 or more, even with load capacitances up to 1000pF. Other key features are 600V VOS and a voltage gain of over 4 million. Each individual amplifier is 100% tested for voltage noise, slew rate and gain bandwidth. The design of the LT1792 has been optimized to achieve true precision performance with an industry standard pinout in the SO-8 package. Specifications are also provided for 5V supplies.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s
s s
Photocurrent Amplifiers Hydrophone Amplifiers High Sensitivity Piezoelectric Accelerometers Low Voltage and Current Noise Instrumentation Amplifier Front Ends Two and Three Op Amp Instrumentation Amplifiers Active Filters
TYPICAL APPLICATIO
Low Noise Hydrophone Amplifier with DC Servo
5V TO 15V
1kHz Input Noise Voltage Distribution
VS = 15V TA = 25C 270 OP AMPS TESTED
LT1792 R2 200 C1*
6 C2 0.47F R4 1M R5 1M
OUTPUT
PERCENT OF UNITS (%)
-5V TO -15V CT HYDROPHONE R6 100k
6
LT1097 3
R7 1M DC OUTPUT 2.5mV FOR TA < 70C OUTPUT VOLTAGE NOISE = 128nV/Hz AT 1kHz (GAIN = 20) C1 CT 100pF TO 5000pF; R4C2 > R8CT; *OPTIONAL
-
R8 100M
+
+
3
-
R1* 100M
R3 3.9k
40
2 7
30
4
20
2
10
0 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 INPUT VOLTAGE NOISE (nV/Hz)
1792 TA02
1792 TA01
U
U
U
1
LT1792 ABSOLUTE AXI U RATI GS
Supply Voltage ..................................................... 20V Differential Input Voltage ...................................... 40V Input Voltage (Equal to Supply Voltage) ............... 20V Output Short-Circuit Duration ........................ Indefinite Operating Temperature Range ............... - 40C to 85C
PACKAGE/ORDER I FOR ATIO
TOP VIEW VOS ADJ 1 -IN A 2 +IN A 3 V
-
ORDER PART NUMBER
8 NC 7V
+
A
6 OUT 5 VOS ADJ N8 PACKAGE 8-LEAD PDIP
4
LT1792ACN8 LT1792CN8 LT1792AIN8 LT1792IN8
TJMAX = 140C, JA = 130C/W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
SYMBOL VOS IOS IB en PARAMETER Input Offset Voltage VS = 5V Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density in RIN Input Noise Current Density Input Resistance Differential Mode Common Mode Input Capacitance VS = 5V Input Voltage Range (Note 5) Common Mode Rejection Ratio Power Supply Rejection Ratio
TA = 25C, VS = 15V, VCM = 0V, unless otherwise noted. (Note 9)
LT1792AC/LT1792AI MIN TYP MAX 0.2 0.4 100 300 2.4 8.3 4.2 10 1011 1011 1010 14 27 13.0 -10.5 13.5 -11.0 105 105 13.0 -10.5 82 83 6.0 0.6 1.0 400 800 LT1792C/LT1792I MIN TYP MAX 0.2 0.4 100 300 2.4 8.3 4.2 10 1011 1011 1010 14 27 13.5 -11.0 100 98 6.0 0.8 1.3 400 800 UNITS mV mV pA pA VP-P nV/Hz nV/Hz fA/Hz pF pF V V dB dB
CONDITIONS (Note 2)
Warmed Up (Note 3) Warmed Up (Note 3) 0.1Hz to 10Hz fO = 10Hz fO = 1000Hz fO = 10Hz, fO = 1000Hz (Note 4)
VCM = -10V to 8V VCM = 8V to 11V
CIN VCM CMRR PSRR
VCM = -10V to 13V VS = 4.5V to 20V
2
U
U
W
WW U
W
(Note 1)
Specified Temperature Range Commercial (Note 8) ......................... - 40C to 85C Industrial ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec) ................ 300C
TOP VIEW VOS ADJ 1 -IN A 2 +IN A 3 V
-
ORDER PART NUMBER
8 NC 7 V+ 6 OUT 5 VOS ADJ
A
4
LT1792ACS8 LT1792CS8 LT1792AIS8 LT1792IS8 S8 PART MARKING 1792A 1792 1792AI 1792I
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 160C, JA = 190C/W
85 88
LT1792
ELECTRICAL CHARACTERISTICS
SYMBOL AVOL VOUT SR GBW IS PARAMETER Large-Signal Voltage Gain Output Voltage Swing Slew Rate Gain-Bandwidth Product Supply Current VS = 5V Offset Voltage Adjustment Range CONDITIONS
TA = 25C, VS = 15V, VCM = 0V, unless otherwise noted.
LT1792AC/LT1792AI MIN TYP MAX 1200 600 13.0 12.0 2.3 4.0 4800 4000 13.2 12.3 3.4 5.6 4.2 4.2 10 5.20 5.15 LT1792C/LT1792I MIN TYP MAX 1000 500 13.0 12.0 2.3 4.0 4500 3000 13.2 12.3 3.4 5.6 4.2 4.2 10 5.20 5.15 UNITS V/mV V/mV V V V/s MHz mA mA mV
VO = 12V, RL = 10k VO = 10V, RL = 1k RL = 10k RL = 1k RL 2k (Note 7) fO = 100kHz
RPOT (to VEE) = 10k
The q denotes specifications which apply over the temperature range 0C TA 70C. VS = 15V, VCM = 0V, unless otherwise noted. (Note 9)
SYMBOL VOS VOS Temp IOS IB VCM CMRR PSRR AVOL VOUT SR GBW IS PARAMETER Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Input Bias Current Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Slew Rate Gain-Bandwidth Product Supply Current VS = 5V VCM = -10V to 12.9V VS = 4.5V to 20V VO = 12V, RL = 10k VO = 10V, RL = 1k RL = 10k RL = 1k RL 2k (Note 7) fO = 100kHz CONDITIONS (Note 2) VS = 5V (Note 6)
q q q q q q q q q q q q q q q q q
MIN
LT1792AC TYP MAX 0.4 0.6 4 180 500 0.8 1.2 10 500 1800
MIN
LT1792C TYP MAX 0.8 1.2 7 180 500 2.7 3.2 40 500 1800
UNITS mV mV V/C pA pA V V dB dB V/mV V/mV V V V/s MHz
12.9 -10.0 81 85 900 500
13.4 -10.8 104 99 3600 2600
12.9 -10.0 79 81 800 400
13.4 -10.8 99 97 3400 2400
12.9 13.2 11.9 12.15 2.1 3.2 3.1 4.5 4.2 4.2 5.30 5.25
12.9 13.2 11.9 12.15 2.1 3.2 3.1 4.5 4.2 4.2 5.30 5.25
mA mA
3
LT1792
ELECTRICAL CHARACTERISTICS
SYMBOL VOS VOS Temp IOS IB VCM CMRR PSRR AVOL VOUT SR GBW IS PARAMETER Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Input Bias Current Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Slew Rate Gain-Bandwidth Product Supply Current VS = 5V
The q denotes specifications which apply over the temperature range - 40C TA 85C. VS = 15V, VCM = 0V, unless otherwise noted. (Notes 8, 9)
LT1792AC/LT1792AI MIN TYP MAX
q q q q q q q
CONDITIONS (Note 2) VS = 5V (Note 6)
LT1792C/LT1792I MIN TYP MAX 1.2 1.5 7 300 1200 12.6 -10.0 78 79 750 300 12.8 11.8 2.0 2.9 13.0 -10.5 98 96 3000 2000 13.1 12.1 3.0 4.3 4.2 4.2 5.40 5.35 3.7 4.2 40 800 4000
UNITS mV mV V/C pA pA V V dB dB V/mV V/mV V V V/s MHz mA mA
0.5 0.8 4 300 1200 12.6 -10.0 80 83 850 400 12.8 11.8 2.0 2.9 13.0 -10.5 103 98 3300 2200 13.1 12.1 3.0 4.3 4.2 4.2
1.0 1.4 10 800 4000
VCM = -10V to 12.6V VS = 4.5V to 20V VO = 12V, RL = 10k VO = 10V, RL = 1k RL = 10k RL = 1k RL 2k fO = 100kHz
q q q q q q q q q q
5.40 5.35
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Typical parameters are defined as the 60% yield of parameter distributions of individual amplifiers. Note 3: Warmed-up IB and IOS readings are extrapolated to a chip temperature of 32C from 25C measurements and 32C characterization data. Note 4: Current noise is calculated from the formula: in = (2qIB)1/2 where q = 1.6 * 10 -19 coulomb. The noise of source resistors up to 200M swamps the contribution of current noise. Note 5: Input voltage range functionality is assured by testing offset voltage at the input voltage range limits to a maximum of 2.3mV (A grade), to 2.8mV (C grade).
Note 6: This parameter is not 100% tested. Note 7: Slew rate is measured in AV = - 1; input signal is 7.5V, output measured at 2.5V. Note 8: The LT1792AC and LT1792C are guaranteed to meet specified performance from 0C to 70C and are designed, characterized and expected to meet these extended temperature limits, but are not tested at - 40C and 85C. The LT1792I is guaranteed to meet the extended temperature limits. The LT1792AC and LT1792AI grade are 100% temperature tested for the specified temperature range. Note 9: The LT1792 is measured in an automated tester in less than one second after application of power. Depending on the package used, power dissipation, heat sinking, and air flow conditions, the fully warmed-up chip temperature can be 10C to 50C higher than the ambient temperature.
4
LT1792
TYPICAL PERFOR A CE CHARACTERISTICS
0.1Hz to 10Hz Voltage Noise
100 RMS VOLTAGE NOISE DENSITY (nV/Hz)
VOLTAGE NOISE (AT 1kHz) (nV/Hz)
VOLTAGE NOISE (1V/DIV)
0
2
6 4 TIME (SEC)
Input Bias and Offset Current Over the Common Mode Range
400 INPUT BIAS AND OFFSET CURRENTS (pA)
INPUT BIAS AND OFFSET CURRENT (nA)
COMMON MODE LIMIT REFERRED TO POWER SUPPLY (V)
TA = 25C VS = 15V NOT WARMED UP
300
200 BIAS CURRENT 100 OFFSET CURRENT 0 -15 10 -10 -5 0 5 COMMON-MODE RANGE (V) 15
1792 G22
Common Mode Rejection Ratio vs Frequency
120
COMMON MODE REJECTION RATIO (dB) POWER SUPPLY REJECTION RATIO (dB)
100 80 60 40 20 0 1k 10k
80 +PSRR 60 -PSRR 40 20 0
VOLTAGE GAIN (dB)
100k 1M FREQUENCY (Hz)
UW
8 10
1792 G01
Voltage Noise vs Frequency
VS = 15V TA = 25C
10 9 8 7 6 5 4 3 2 1
Voltage Noise vs Chip Temperature
VS = 15V
10
1/f CORNER 30Hz
1 1 10 100 1k FREQUENCY (Hz) 10k
1792 G02
0 -75 -50 -25 0 25 50 75 TEMPERATURE (C)
100 125
1792 G03
Input Bias and Offset Current vs Chip Temperature
100 30 10 3 1 IB 0.3 IOS 0.1 0.03 0.01 - 75 - 50 - 25 0 25 50 75 TEMPERATURE (C) 100 125
1792 G04
Common Mode Limit vs Temperature
V+ 0 - 0.5 -1.0 -1.5 - 2.0 V + = 5V TO 20V
VS = 15V
4.0 3.5 3.0 2.5 V - = - 5V TO - 20V
V -+ 2.0 - 60
-20
60 100 20 TEMPERATURE (C)
140
1792 G05
Power Supply Rejection Ratio vs Frequency
120 TA = 25C 100
180 160 140 120 100 80 60 40 20 0
Voltage Gain vs Frequency
TA = 25C VS = 15V
10M
1792 G06
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
1792 G07
- 20 0.01
1
10k 100 FREQUENCY (Hz)
1M
100M
1792 G08
5
LT1792
TYPICAL PERFOR A CE CHARACTERISTICS
Gain and Phase Shift vs Frequency
50 40
VOLTAGE GAIN (dB)
PHASE
TA = 25C VS = 15V CL = 10pF
20 GAIN 10 0 -10 0.1 1 10 FREQUENCY (MHz)
140 160 180 200 100
1792 G09
5V/DIV
30
120
20mV/DIV
Output Voltage Swing vs Load Current
V + - 0.8 -1.0 25C -55C 125C
OUTPUT VOLTAGE SWING (V)
-1.2 - 1.4 -1.6 2.0 1.8 1.6 1.4 1.2 -55C 125C
SLEW RATE (V/s)
OVERSHOOT (%)
VS = 5V TO 20V
25C
V - +1.0 -10 -8 -6 -4 -2 0 2 4 6 8 10 ISINK ISOURCE OUTPUT CURRENT (mA)
1792 G12
Warm-Up Drift
TOTAL HARMONIC DISTROTION + NOISE (%)
TOTAL HARMONIC DISTROTION + NOISE (%)
90 CHANGE IN OFFSET VOLTAGE (V) 75 60 45
VS = 15V TA = 25C SO-8 PACKAGE
N8 PACKAGE 30 15 0
0
5 2 3 4 1 TIME AFTER POWER ON (MINUTES)
6
UW
6
1792 G15
Small-Signal Transient Response
80 100
PHASE SHIFT (DEG)
Large-Signal Transient Response
AV = 1 CL = 10pF VS = 15V, 5V
1s/DIV
1792 G10
AV = 1 CL = 10pF RL = 2k VS = 15V
5s/DIV
1792 G11
Capacitive Load Handling
50 VS = 15V TA = 25C RL 10k VO = 100mVP-P AV = 10 RF = 10k CF = 20pF
6 5 4
Slew Rate and Gain-Bandwidth Product vs Temperature
GAIN-BANDWIDTH PRODUCT (fO = 100kHz) (MHz)
VS = 15V 12 10 8 SR 3 2 1 GBWP 6 4 2 0 100 125
1792 G14
40
30
20 AV = 1 10 AV = 10 0 0.1 1 100 1000 10 CAPACITIVE LOAD (pF) 10000
1792 G13
0 25 50 75 - 75 - 50 - 25 0 TEMPERATURE (C)
THD and Noise vs Frequency for Noninverting Gain
1 1 ZL = 2k 15pF VO = 20VP-P AV = 1, 10, 100 MEASUREMENT BANDWIDTH = 10Hz TO 80kHz
THD and Noise vs Frequency for Inverting Gain
ZL = 2k 15pF VO = 20VP-P AV = - 1, - 10, - 100 MEASUREMENT BANDWIDTH = 10Hz TO 80kHz
0.1
0.1
0.01
AV = 100
0.01
AV = - 100 AV = - 10
0.001
AV = 10 NOISE FLOOR 20 100 1k FREQUENCY (Hz)
AV = 1
0.001 NOISE FLOOR 20 100 1k FREQUENCY (Hz)
AV = - 1
0.0001 10k 20k
1792 G16
0.0001 10k 20k
1792 G17
LT1792
TYPICAL PERFOR A CE CHARACTERISTICS
THD and Noise vs Output Amplitude for Noninverting Gain
TOTAL HARMONIC DISTORTION + NOISE (%) ZL = 2k 15pF, fO = 1kHz AV = 1, 10, 100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz AV = 100 0.01 AV = 10 0.001 AV = 1
TOTAL HARMONIC DISTORTION + NOISE (%)
1
0.1
0.0001 0.3 1 10 OUTPUT SWING (VP-P) 30
1792 G18
Short-Circuit Output Current vs Temperature
40 35 VS = 15V 5
OUTPUT CURRENT (mA)
30 SINK 25 20 15 10 - 75 - 50 - 25 0 25 50 75 TEMPERATURE (C) SOURCE
SUPPLY CURRENT (mA)
APPLICATI
S I FOR ATIO
6 5 1 50k - 15V
1792 F01a
VOS = 10mV
Being a low voltage noise JFET op amp, the LT1792 can replace many bipolar op amps that are used in amplifying low level signals from high impedance transducers. The
(a) Figure 1
+
+
3
4
3
-
-
The LT1792 may be inserted directly into OPA124, AD743, AD745, AD645, AD544 and AD820 sockets with improved noise performance. Offset nulling will be compatible with these devices with the wiper of the potentiometer tied to the negative supply (Figure 1a). No appreciable change in offset voltage drift with temperature will occur when the device is nulled with a potentiometer ranging from 10k to 200k. Finer adjustments can be made with resistors in series with the potentiometer (Figure 1b).
U
W
UW
THD and Noise vs Output Amplitude for Inverting Gain
1 ZL = 2k 15pF, fO = 1kHz AV = - 1, - 10, - 100 MEASUREMENT BANDWIDTH = 10Hz TO 22kHz AV = -100 0.01 AV = -10 0.001 AV = -1
0.1
0.0001 0.3 1 10 OUTPUT SWING (VP-P) 30
1792 G19
Supply Current vs Temperature
VS = 15V 4 VS = 5V
100 125
1792 G20
3 - 75 - 50 - 25 0 25 50 75 TEMPERATURE (C)
100 125
1792 G21
U
UO
15V 2 7
15V 2 7 6 4 5 1 10k 10k VOS = 1mV
50k - 15V
1792 F01b
(b)
7
LT1792
APPLICATI S I FOR ATIO
best bipolar op amps, with higher current noise, will eventually lose out to the LT1792 when transducer impedance increases. The low voltage noise of the LT1792 allows it to surpass most single JFET op amps available. For the best performance versus area available anywhere, the LT1792 is offered in the SO-8 surface mount package with no degradation in performance. The low voltage and current noise offered by the LT1792 makes it useful in a wide range of applications, especially where high impedance, capacitive transducers are used such as hydrophones, precision accelerometers and photo diodes. The total output noise in such a system is the gain times the RMS sum of the op amp input referred voltage noise, the thermal noise of the transducer, and the op amp bias current noise times the transducer impedance. Figure 2 shows total input voltage noise versus source resistance. In a low source resistance (<5k) application the op amp voltage noise will dominate the total noise. This means the LT1792 will beat out any JFET op amp, only the lowest noise bipolar op amps have the edge at low source resistances. As the source resistance increases from 5k to 50k, the LT1792 will match the best bipolar op amps for noise performance, since the thermal noise of the transducer (4kTR) begins to dominate the total noise. A further increase in source resistance, above 50k, is where the op amp's current noise component (2qIB RTRANS) will eventually dominate the total noise. At these high source resistances, the LT1792 will out perform the lowest noise bipolar op amp due to the inherently low
R2 CB
INPUT NOISE VOLTAGE (nV/Hz)
R1
OUTPUT
CS
RS
CS
RS
CB CS RB = RS RS > R1 OR R2
TRANSDUCER
CB
RB
TRANSDUCER
1792 F03
Figure 3. Noninverting and Inverting Gain Configurations
8
+
-
+
-
RB
U
1k LT1007*
CS RS
W
U
UO
LT1792*
100
- +
VO RS CS
LT1007
10 LT1792 LT1007 1 100
LT1792
RESISTOR NOISE ONLY 1k 10k 100k 1M 10M SOURCE RESISTANCE () 100M
1792 F02
SOURCE RESISTANCE = 2RS = R * PLUS RESISTOR PLUS RESISTOR 1000pF CAPACITOR Vn = AV Vn2(OP AMP) + 4kTR + 2qIB * R2
Figure 2. Comparison of LT1792 and LT1007 Total Output 1kHz Voltage Noise Versus Source Resistance
current noise of FET input op amps. Clearly, the LT1792 will extend the range of high impedance transducers that can be used for high signal-to-noise ratios. This makes the LT1792 the best choice for high impedance, capacitive transducers. The high input impedance JFET front end makes the LT1792 suitable in applications where very high charge sensitivity is required. Figure 3 illustrates the LT1792 in its inverting and noninverting modes of operation. A charge amplifier is shown in the inverting mode example; here the gain depends on the principal of charge conservation at
RF CF
OUTPUT
CB = CF CS RB = RF RS dQ dV Q = CV; = I = C dt dt
LT1792
APPLICATI
S I FOR ATIO
the input of the LT1792. The charge across the transducer capacitance, CS, is transferred to the feedback capacitor CF, resulting in a change in voltage, dV, equal to dQ/CF. The gain therefore is CF/CS. For unity gain, the CF should equal the transducer capacitance plus the input capacitance of the LT1792 and RF should equal RS. In the noninverting mode example, the transducer current is converted to a change in voltage by the transducer capacitance; this voltage is then buffered by the LT1792 with a gain of 1 + R1/R2. A DC path is provided by RS, which is either the transducer impedance or an external resistor. Since RS is usually several orders of magnitude greater than the parallel combination of R1 and R2, RB is added to balance the DC offset caused by the noninverting input bias current and RS. The input bias currents, although small at room temperature, can create significant errors at higher temperature, especially with transducer resistances of up to 100M or more. The optimum value for RS is determined by equating the thermal noise (4kTRS) to the current noise times RS, [(2qIB) * RS], resulting in RB = 2VT/IB (VT = 26mV at 25C). A parallel capacitor, CB, is used to cancel the phase shift caused by the op amp input capacitance and RB. Reduced Power Supply Operation The LT1792 can be operated from 5V supplies for lower power dissipation resulting in lower IB and noise at the
INPUT: 5.2V Sine Wave
1792 F04a
Figure 4. Voltage Follower with Input Exceeding the Common Mode Range ( VS = 5V)
U
expense of reduced dynamic range. To illustrate this benefit, let's take the following example: An LT1792CS8 operates at an ambient temperature of 25C with 15V supplies, dissipating 159mW of power (typical supply current = 5.3mA). The SO-8 package has a JA of 190C/W, which results in a die temperature increase of 30.2C or a room temperature die operating temperature of 55.2C. At 5V supplies, the die temperature increases by only one third of the previous amount or 10.1C resulting in a typical die operating temperature of only 35.1C. A 20 degree reduction of die temperature is achieved at the expense of a 20V reduction in dynamic range. To take full advantage of a wide input common mode range, the LT1792 was designed to eliminate phase reversal. Referring to the photographs shown in Figure 4, the LT1792 is shown operating in the follower mode (AV = 1) at 5V supplies with the input swinging 5.2V. The output of the LT1792 clips cleanly and recovers with no phase reversal. This has the benefit of preventing lock-up in servo systems and minimizing distortion components. High Speed Operation The low noise performance of the LT1792 was achieved by making the input JFET differential pair large to maximize the first stage gain. Increasing the JFET geometry
LT1792 Output
1792 F03b
W
U
UO
9
LT1792
APPLICATI S I FOR ATIO
also increases the parasitic gate capacitance, which if left unchecked, can result in increased overshoot and ringing. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance and capacitance (RS, CS), and the amplifier input capacitance (CIN = 27pF). In low gain configurations and with RS and RF in the kilohm range (Figure 5), this pole can create excess phase shift and even oscillation. A small capacitor (CF) in parallel with RF eliminates this problem. With RS(CS + CIN) = RFCF, the effect of the feedback pole is completely removed.
RS
CS
Figure 5
TYPICAL APPLICATI
S
Accelerometer Amplifier with DC Servo
C1 1250pF
R1 100M
R3 2k
C2 2F
R2 18k R4 20M R5 20M C3 2F R4C2 = R5C3 > R1 (1 + R2/R3) C1 OUTPUT = 0.8mV/pC* = 8.0mV/g** DC OUTPUT 2.7mV OUTPUT NOISE = 6nV/H AT 1kHz z *PICOCOULOMBS **g = EARTH'S GRAVITATIONAL CONSTANT
2
6 5V TO 15V
LT1792 3
10Hz Fourth Order Chebyshev Lowpass Filter (0.01dB Ripple)
R2 237k 15V C1 33nF R5 154k
VIN C2 100nF
LT1792
-15V
TYPICAL OFFSET 0.8mV 1% TOLERANCES FOR VIN = 10VP-P, VOUT = -121dB AT f > 330Hz = - 6dB AT f = 16.3Hz LOWER RESISTOR VALUES WILL RESULT IN LOWER THERMAL NOISE AND LARGER CAPACITORS
10
+
+
3
4
C4 330nF
3
-
-
R1 237k
R3 249k
+
3
-
ACCELEROMETER B & K MODEL 4381 OR EQUIVALENT
2
7 LT1792 4 6
OUTPUT
1792 TA03
- 5V TO -15V
C3 10nF
2
7 6
R4 154k
R6 249k
2
LT1792
+
-
-
+
U
CF RF CIN OUTPUT
1792 F05
W
UO
U
UO
6
VOUT
1792 TA06
LT1792
TYPICAL APPLICATI UO
CD D1 1N914 2N3904 R3 1k
S
Low Noise Light Sensor with DC Servo
C1 2pF R1 1M 2
D2 1N914
6
LT1792 3 4
HAMAMATSU S1336-5BK V-
R5 1k
R4 1k
R2C2 > C1R1 CD = PARASITIC PHOTODIODE CAPACITANCE VO = 100mV/WATT FOR 200nm WAVE LENGTH 330mV/WATT FOR 633nm WAVE LENGTH
1792 TA05
V-
Paralleling Amplifiers to Reduce Voltage Noise
3
+
An LT1792 6
1k
2 51
-
1k 10k
3
+
A2 LT1792 6
2 51
-
1k 15V 3
3
+ -
7 6 1k
2
A1 LT1792 4 -15V 1k
51
1. ASSUME VOLTAGE NOISE OF LT1792 AND 51 SOURCE RESISTOR = 4.3nV/Hz 2. GAIN WITH n LT1792s IN PARALLEL = n x 200 3. OUTPUT NOISE = n x 200 x 4.3nV/ z H OUTPUT NOISE 4.3 4. INPUT REFERRED NOISE = = nV/ z H n x 200 n 5. NOISE CURRENT AT INPUT INCREASES n TIMES 1792 TA04
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
+
-
1k
2
-
+
+
V+ 7
3
-
LT1792 6 C2 0.022F OUTPUT 2 R2 100k 15V 7 LT1792 4 -15V 6 OUTPUT
11
LT1792
TYPICAL APPLICATI
Light Balance Detection Circuit
R1 1M C1 2pF TO 8pF
I1 PD1 I2 PD2
LT1792
VOUT
VIN
1792 TA07
VOUT = 1M x (I1 - I2) PD1,PD2 = HAMAMATSU S1336-5BK WHEN EQUAL LIGHT ENTERS PHOTODIODES, VOUT < 3mV.
C1 = CL 0.1F OUTPUT SHORT-CIRCUIT CURRENT ( 30mA) WILL LIMIT THE RATE AT WHICH THE VOLTAGE CAN CHANGE ACROSS LARGE CAPACITORS I=C
()
dV dt
PACKAGE DESCRIPTIO
(LTC DWG # 05-08-1510)
0.400* (10.160) MAX 8 7 6
Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 7 6
N8 Package 8-Lead PDIP (Narrow 0.300)
5
0.255 0.015* (6.477 0.381)
1 0.300 - 0.325 (7.620 - 8.255)
2
3
4 0.130 0.005 (3.302 0.127)
1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.053 - 0.069 (1.346 - 1.752) 0- 8 TYP 2 3 4
0.045 - 0.065 (1.143 - 1.651)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076) N8 1197
(
+0.035 0.325 -0.015 +0.889 8.255 -0.381
)
0.100 0.010 (2.540 0.254)
0.014 - 0.019 (0.355 - 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 - 0.050 0.406 - 1.270
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
RELATED PARTS
PART NUMBER LT1113 LT1169 LT1793 DESCRIPTION Low Noise Dual JFET Op Amp Low Noise Dual JFET Op Amp Low Noise Single Op Amp COMMENTS Dual Version of LT1792, VNOISE = 4.5nV/Hz Dual Version of LT1793, IB = 10pA, VNOISE = 6nV/Hz Lower IB Version of LT1792, IB = 10pA, VNOISE = 6nV/Hz
1792f LTTP 0599 4K * PRINTED IN USA
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
+
-
U
UO
S
Unity-Gain Buffer with Extended Load Capacitance Drive Capability
R2 1k C1
R1 33 VOUT CL
1792 TA08
LT1792
+
8 0.228 - 0.244 (5.791 - 6.197)
-
5
0.150 - 0.157** (3.810 - 3.988)
0.004 - 0.010 (0.101 - 0.254)
0.050 (1.270) TYP SO8 0996
(c) LINEAR TECHNOLOGY CORPORATION 1999

▲Up To Search▲

Price & Availability of LT1792

	To Download LT1792 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .